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stm32 /stm32wb /STM32WB55_CM0P /RCC /APB2SMENR

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Interpret as APB2SMENR

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https://regviz.com/r/stm32/stm32wb/STM32WB10_CM4/RCC/APB2SMENR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM1SMEN)TIM1SMEN 0 (SPI1SMEN)SPI1SMEN 0 (USART1SMEN)USART1SMEN 0 (TIM16SMEN)TIM16SMEN 0 (TIM17SMEN)TIM17SMEN 0 (SAI1SMEN)SAI1SMEN

Description

APB2SMENR

Fields

TIM1SMEN

TIM1 timer clocks enable during CPU1 Sleep mode
SPI1SMEN

SPI1 clocks enable during CPU1 Sleep mode
USART1SMEN

USART1clocks enable during CPU1 Sleep mode
TIM16SMEN

TIM16 timer clocks enable during CPU1 Sleep mode
TIM17SMEN

TIM17 timer clocks enable during CPU1 Sleep mode
SAI1SMEN

SAI1 clocks enable during CPU1 Sleep mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32