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stm32 /stm32wb /STM32WB55_CM0P /RCC /PLLSAI1CFGR

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Interpret as PLLSAI1CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLLN0 (PLLPEN)PLLPEN 0PLLP0 (PLLQEN)PLLQEN 0PLLQ0 (PLLREN)PLLREN 0PLLR

Description

PLLSAI1 configuration register

Fields

PLLN

SAIPLL multiplication factor for VCO
PLLPEN

SAIPLL PLLSAI1CLK output enable
PLLP

SAI1PLL division factor P for PLLSAICLK (SAI1clock)
PLLQEN

SAIPLL PLLSAIUSBCLK output enable
PLLQ

SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
PLLREN

PLLSAI PLLADC1CLK output enable
PLLR

PLLSAI division factor R for PLLADC1CLK (ADC clock)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32