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stm32 /stm32wb /STM32WB55_CM0P /SAI1 /BSR

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Interpret as BSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OVRUDR)OVRUDR 0 (MUTEDET)MUTEDET 0 (WCKCFG)WCKCFG 0 (FREQ)FREQ 0 (CNRDY)CNRDY 0 (AFSDET)AFSDET 0 (LFSDET)LFSDET 0FLVL

Description

BStatus register

Fields

OVRUDR

Overrun / underrun
MUTEDET

Mute detection
WCKCFG

Wrong clock configuration flag
FREQ

FIFO request
CNRDY

Codec not ready
AFSDET

Anticipated frame synchronization detection
LFSDET

Late frame synchronization detection
FLVL

FIFO level threshold

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32