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stm32 /stm32wb /STM32WB55_CM0P /SPI1 /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXNE)RXNE 0 (TXE)TXE 0 (CRCERR)CRCERR 0 (MODF)MODF 0 (OVR)OVR 0 (BSY)BSY 0 (TIFRFE)TIFRFE 0FRLVL 0FTLVL

Description

status register

Fields

RXNE

Receive buffer not empty
TXE

Transmit buffer empty
CRCERR

CRC error flag
MODF

Mode fault
OVR

Overrun flag
BSY

Busy flag
TIFRFE

TI frame format error
FRLVL

FIFO reception level
FTLVL

FIFO transmission level

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32