Regviz

stm32 /stm32wb /STM32WB55_CM4 /PWR /SCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb/STM32WB10_CM4/PWR/SCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CWUF1)CWUF1 0 (CWUF2)CWUF2 0 (CWUF3)CWUF3 0 (CWUF4)CWUF4 0 (CWUF5)CWUF5 0 (CSMPSFBF)CSMPSFBF 0 (CBORHF)CBORHF 0 (CBLEWUF)CBLEWUF 0 (C802WUF)C802WUF 0 (CCRPEF)CCRPEF 0 (CBLEAF)CBLEAF 0 (C802AF)C802AF 0 (CC2HF)CC2HF

Description

Power status clear register

Fields

CWUF1

Clear wakeup flag 1
CWUF2

Clear wakeup flag 2
CWUF3

Clear wakeup flag 3
CWUF4

Clear wakeup flag 4
CWUF5

Clear wakeup flag 5
CSMPSFBF

Clear SMPS Step Down converter forced in Bypass interrupt flag
CBORHF

Clear BORH interrupt flag
CBLEWUF

Clear BLE wakeup interrupt flag
C802WUF

Clear 802.15.4 wakeup interrupt flag
CCRPEF

Clear critical radio phase end of activity interrupt flag
CBLEAF

Clear BLE end of activity interrupt flag
C802AF

Clear 802.15.4 end of activity interrupt flag
CC2HF

Clear CPU2 Hold interrupt flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32