Regviz

stm32 /stm32wb /STM32WB55_CM4 /RCC /C2AHB2SMENR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as C2AHB2SMENR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb/STM32WB10_CM4/RCC/C2AHB2SMENR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GPIOASMEN)GPIOASMEN 0 (GPIOBSMEN)GPIOBSMEN 0 (GPIOCSMEN)GPIOCSMEN 0 (GPIODSMEN)GPIODSMEN 0 (GPIOESMEN)GPIOESMEN 0 (GPIOHSMEN)GPIOHSMEN 0 (ADCFSSMEN)ADCFSSMEN 0 (AES1SMEN)AES1SMEN

Description

CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register

Fields

GPIOASMEN

CPU2 IO port A clocks enable during Sleep and Stop modes
GPIOBSMEN

CPU2 IO port B clocks enable during Sleep and Stop modes
GPIOCSMEN

CPU2 IO port C clocks enable during Sleep and Stop modes
GPIODSMEN

CPU2 IO port D clocks enable during Sleep and Stop modes
GPIOESMEN

CPU2 IO port E clocks enable during Sleep and Stop modes
GPIOHSMEN

CPU2 IO port H clocks enable during Sleep and Stop modes
ADCFSSMEN

CPU2 ADC clocks enable during Sleep and Stop modes
AES1SMEN

CPU2 AES1 accelerator clocks enable during Sleep and Stop modes

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32