stm32 /stm32wb /STM32WB55_CM4 /RCC /CR

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Interpret as CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MSION)MSION 0 (MSIRDY)MSIRDY 0 (MSIPLLEN)MSIPLLEN 0MSIRANGE 0 (HSION)HSION 0 (HSIKERON)HSIKERON 0 (HSIRDY)HSIRDY 0 (HSIASFS)HSIASFS 0 (HSIKERDY)HSIKERDY 0 (HSEON)HSEON 0 (HSERDY)HSERDY 0 (HSEBYP)HSEBYP 0 (CSSON)CSSON 0 (HSEPRE)HSEPRE 0 (PLLON)PLLON 0 (PLLRDY)PLLRDY 0 (PLLSAI1ON)PLLSAI1ON 0 (PLLSAI1RDY)PLLSAI1RDY

Description

Clock control register

Fields

MSION

MSI clock enable

MSIRDY

MSI clock ready flag

MSIPLLEN

MSI clock PLL enable

MSIRANGE

MSI clock ranges

HSION

HSI clock enabled

HSIKERON

HSI always enable for peripheral kernels

HSIRDY

HSI clock ready flag

HSIASFS

HSI automatic start from Stop

HSIKERDY

HSI kernel clock ready flag for peripherals requests

HSEON

HSE clock enabled

HSERDY

HSE clock ready flag

HSEBYP

HSE crystal oscillator bypass

CSSON

HSE Clock security system enable

HSEPRE

HSE sysclk and PLL M divider prescaler

PLLON

Main PLL enable

PLLRDY

Main PLL clock ready flag

PLLSAI1ON

SAI1 PLL enable

PLLSAI1RDY

SAI1 PLL clock ready flag

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