PLLCFGR

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Interpret as PLLCFGR

PLLSYS configuration register

PLLSRC	Main PLL, PLLSAI1 and PLLSAI2 entry clock source
PLLM	Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
PLLN	Main PLLSYS multiplication factor N
PLLPEN	Main PLLSYSP output enable
PLLP	Main PLL division factor P for PPLSYSSAICLK
PLLQEN	Main PLLSYSQ output enable
PLLQ	Main PLLSYS division factor Q for PLLSYSUSBCLK
PLLREN	Main PLLSYSR PLLCLK output enable
PLLR	Main PLLSYS division factor R for SYSCLK (system clock)

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