Regviz

stm32 /stm32wb /STM32WB55_CM4 /TIM17 /TISEL

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Interpret as TISEL

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https://regviz.com/r/stm32/stm32wb/STM32WB55_CM0P/TIM17/TISEL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1SEL

Description

input selection register

Fields

TI1SEL

selects TI1[0] to TI1[15] input

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32