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stm32 /stm32wb0 /STM32WB05 /BLUE_REG /INTERRUPT1LATENCYREG

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Interpret as INTERRUPT1LATENCYREG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTERRUPT1LATENCY

Description

INTERRUPT1LATENCYREG register

Fields

INTERRUPT1LATENCY

relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32