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stm32 /stm32wb0 /STM32WB05 /SYSTEM_CTRL /I2C_FMP_CTRL

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Interpret as I2C_FMP_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (I2C1_PA0_FMP)I2C1_PA0_FMP 0 (I2C1_PA1_FMP)I2C1_PA1_FMP 0 (I2C1_PB6_FMP)I2C1_PB6_FMP 0 (I2C1_PB7_FMP)I2C1_PB7_FMP

Description

I2C_FMP_CTRL register

Fields

I2C1_PA0_FMP

I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. 0: PA0 pin operated in standard mode. 1: FM+ mode is enabled on PA0 pin, and speed control is bypassed
I2C1_PA1_FMP

I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. 0: PA1 pin operated in standard mode. 1: FM+ mode is enabled on PA1 pin, and speed control is bypassed
I2C1_PB6_FMP

I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. 0: PB6 pin operated in standard mode. 1: FM+ mode is enabled on PB6 pin, and speed control is bypassed.
I2C1_PB7_FMP

I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. 0: PB7 pin operated in standard mode. 1: FM+ mode is enabled on PB7 pin, and speed control is bypassed

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32