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stm32 /stm32wb0 /STM32WB06 /FLASH_CTRL /IRQRAW

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Interpret as IRQRAW

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMDDONE_RIS)CMDDONE_RIS 0 (CMDSTART_RIS)CMDSTART_RIS 0 (CMDERR_RIS)CMDERR_RIS 0 (ILLCMD_RIS)ILLCMD_RIS 0 (READOK_RIS)READOK_RIS

Description

IRQRAW register

Fields

CMDDONE_RIS

Command done raw/unmasked interrupt status. This it is set once the requested command execution is completed. Cleared by writing 1.
CMDSTART_RIS

Command started raw/unmasked interrupt status. This bit is set once the requested command execution has started.
CMDERR_RIS

Command error raw/unmasked interrupt status
ILLCMD_RIS

Illegal command raw/unmasked interrupt status.
READOK_RIS

Mass read OK raw/unmasked interrupt status

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32