Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/stm32/stm32wb0/STM32WB06/RADIO/ANTSW0_DIG_USR#0x0
ANTSW0_DIG_USR register
specifies the exact timing of the first I/Q sampling in the reference period.
https://github.com/modm-io/cmsis-svd-stm32