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stm32 /stm32wb0 /STM32WB06 /RCC /AHBENR

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Interpret as AHBENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DMAEN 0 (GPIOAEN)GPIOAEN 0 (GPIOBEN)GPIOBEN 0 (B_0x0)CRCEN 0 (B_0x0)PKAEN 0 (B_0x0)RNGEN

DMAEN=B_0x0, RNGEN=B_0x0, PKAEN=B_0x0, CRCEN=B_0x0

Description

AHBENR register

Fields

DMAEN

DMA and DMAMUX enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
GPIOAEN

GPIOA enable. It must be enabled by default
GPIOBEN

GPIOB enable. It must be enabled by default
CRCEN

CRC enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
PKAEN

PKA clock enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
RNGEN

RNG clock enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32