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stm32 /stm32wb0 /STM32WB06 /RNG /RNG_SR

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Interpret as RNG_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RNGRDY 0 (B_0x0)REVCLK 0 (B_0x0)FAULT

REVCLK=B_0x0, RNGRDY=B_0x0, FAULT=B_0x0

Description

RNG_SR register

Fields

RNGRDY

New random value ready

0 (B_0x0): Normal operation.

1 (B_0x1): RNG is disabled.
REVCLK

RNGCLK clock reveal bit.

0 (B_0x0): At least one oscillator is ON

1 (B_0x1): All oscillators are down
FAULT

Fault reveal bit.

0 (B_0x0): Internal clock for RNG clock is present.

1 (B_0x1): Internal RNG clock is not present.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32