stm32 /stm32wb0 /STM32WB06 /SPI2 /SPI2_CR2

Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.

• 0: Rx buffer DMA disabled
• 1: Rx buffer DMA enabled

Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.

• 0: Tx buffer DMA disabled
• 1: Tx buffer DMA enabled

SS output enable

• 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration
• 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment.

NSS pulse management This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1.

• 0: No NSS pulse
• 1: NSS pulse generated

Frame format

• 0: SPI Motorola mode
• 1 SPI TI mode

Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).

• 0: Error interrupt is masked
• 1: Error interrupt is enabled

RX buffer not empty interrupt enable

• 0: RXNE interrupt masked
• 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set.

Tx buffer empty interrupt enable

• 0: TXE interrupt masked
• 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.

Data size These bits configure the data length for SPI transfers:

• 0000: Not used
• 0001: Not used
• 0010: Not used
• 0011: 4-bit
• 0100: 5-bit
• 0101: 6-bit
• 0110: 7-bit
• 0111: 8-bit
• 1000: 9-bit
• 1001: 10-bit
• 1010: 11-bit
• 1011: 12-bit
• 1100: 13-bit
• 1101: 14-bit
• 1110: 15-bit
• 1111: 16-bit If software attempts to write one of the Not used values, they are forced to the value 0111(8-bit).

FIFO reception threshold FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. This bit is used to set the threshold of the RXFIFO that triggers an RXNE event

• 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
• 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).

• 0: Number of data to transfer is even
• 1: Number of data to transfer is odd

Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).

• 0: Number of data to transfer is even
• 1: Number of data to transfer is odd