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stm32 /stm32wb0 /STM32WB07 /ADC /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADC_ON_OFF)ADC_ON_OFF 0 (START_CON)START_CON 0 (STOP_OP_MOD)STOP_OP_MOD 0 (DIG_AUD_MODE)DIG_AUD_MODE 0 (TEST_MODE)TEST_MODE 0 (ADC_LDO_ENA)ADC_LDO_ENA

Description

ADC control register

Fields

ADC_ON_OFF

ADC_ON_OFF:

– 0: power off the ADC

– 1: power on the ADC
START_CON

generate a start pulse to initiate an ADC conversion
STOP_OP_MOD

stop the on-going OP_MODE (ADC mode, Analog audio mode, Full
DIG_AUD_MODE

enable the digital audio mode (the data path uses the decimation filter)
TEST_MODE

select the functional or the test mode of the ADC
ADC_LDO_ENA

enable the LDO associated to the ADC block

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32