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stm32 /stm32wb0 /STM32WB07 /GPIOA /GPIOA_AFRL

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Interpret as GPIOA_AFRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)AFR00 (B_0x0)AFR10 (B_0x0)AFR20 (B_0x0)AFR30 (B_0x0)AFR40 (B_0x0)AFR50 (B_0x0)AFR60 (B_0x0)AFR7

AFR5=B_0x0, AFR0=B_0x0, AFR4=B_0x0, AFR2=B_0x0, AFR6=B_0x0, AFR3=B_0x0, AFR1=B_0x0, AFR7=B_0x0

Description

GPIO alternate function low register

Fields

AFR0

Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os.

0 (B_0x0): AF0

1 (B_0x1): AF1

2 (B_0x2): AF2

3 (B_0x3): AF3

4 (B_0x4): AF4

5 (B_0x5): AF5

6 (B_0x6): AF6

7 (B_0x7): AF7

8 (B_0x8): AF8

9 (B_0x9): AF9

10 (B_0xA): AF10

11 (B_0xB): AF11

12 (B_0xC): AF12

13 (B_0xD): AF13

14 (B_0xE): AF14

15 (B_0xF): AF15
AFR1

Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os.

0 (B_0x0): AF0

1 (B_0x1): AF1

2 (B_0x2): AF2

3 (B_0x3): AF3

4 (B_0x4): AF4

5 (B_0x5): AF5

6 (B_0x6): AF6

7 (B_0x7): AF7

8 (B_0x8): AF8

9 (B_0x9): AF9

10 (B_0xA): AF10

11 (B_0xB): AF11

12 (B_0xC): AF12

13 (B_0xD): AF13

14 (B_0xE): AF14

15 (B_0xF): AF15
AFR2

Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os.

0 (B_0x0): AF0

1 (B_0x1): AF1

2 (B_0x2): AF2

3 (B_0x3): AF3

4 (B_0x4): AF4

5 (B_0x5): AF5

6 (B_0x6): AF6

7 (B_0x7): AF7

8 (B_0x8): AF8

9 (B_0x9): AF9

10 (B_0xA): AF10

11 (B_0xB): AF11

12 (B_0xC): AF12

13 (B_0xD): AF13

14 (B_0xE): AF14

15 (B_0xF): AF15
AFR3

Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os.

0 (B_0x0): AF0

1 (B_0x1): AF1

2 (B_0x2): AF2

3 (B_0x3): AF3

4 (B_0x4): AF4

5 (B_0x5): AF5

6 (B_0x6): AF6

7 (B_0x7): AF7

8 (B_0x8): AF8

9 (B_0x9): AF9

10 (B_0xA): AF10

11 (B_0xB): AF11

12 (B_0xC): AF12

13 (B_0xD): AF13

14 (B_0xE): AF14

15 (B_0xF): AF15
AFR4

Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os.

0 (B_0x0): AF0

1 (B_0x1): AF1

2 (B_0x2): AF2

3 (B_0x3): AF3

4 (B_0x4): AF4

5 (B_0x5): AF5

6 (B_0x6): AF6

7 (B_0x7): AF7

8 (B_0x8): AF8

9 (B_0x9): AF9

10 (B_0xA): AF10

11 (B_0xB): AF11

12 (B_0xC): AF12

13 (B_0xD): AF13

14 (B_0xE): AF14

15 (B_0xF): AF15
AFR5

Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os.

0 (B_0x0): AF0

1 (B_0x1): AF1

2 (B_0x2): AF2

3 (B_0x3): AF3

4 (B_0x4): AF4

5 (B_0x5): AF5

6 (B_0x6): AF6

7 (B_0x7): AF7

8 (B_0x8): AF8

9 (B_0x9): AF9

10 (B_0xA): AF10

11 (B_0xB): AF11

12 (B_0xC): AF12

13 (B_0xD): AF13

14 (B_0xE): AF14

15 (B_0xF): AF15
AFR6

Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os.

0 (B_0x0): AF0

1 (B_0x1): AF1

2 (B_0x2): AF2

3 (B_0x3): AF3

4 (B_0x4): AF4

5 (B_0x5): AF5

6 (B_0x6): AF6

7 (B_0x7): AF7

8 (B_0x8): AF8

9 (B_0x9): AF9

10 (B_0xA): AF10

11 (B_0xB): AF11

12 (B_0xC): AF12

13 (B_0xD): AF13

14 (B_0xE): AF14

15 (B_0xF): AF15
AFR7

Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os.

0 (B_0x0): AF0

1 (B_0x1): AF1

2 (B_0x2): AF2

3 (B_0x3): AF3

4 (B_0x4): AF4

5 (B_0x5): AF5

6 (B_0x6): AF6

7 (B_0x7): AF7

8 (B_0x8): AF8

9 (B_0x9): AF9

10 (B_0xA): AF10

11 (B_0xB): AF11

12 (B_0xC): AF12

13 (B_0xD): AF13

14 (B_0xE): AF14

15 (B_0xF): AF15

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32