RD_WRN=B_0x0, NACK=B_0x0, RELOAD=B_0x0, STOP=B_0x0, PECBYTE=B_0x0, ADD10=B_0x0, HEAD10R=B_0x0, AUTOEND=B_0x0, START=B_0x0
I2C control register 2
| SADD | Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don’t care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed. |
| RD_WRN | Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed. 0 (B_0x0): Master requests a write transfer. 1 (B_0x1): Master requests a read transfer. |
| ADD10 | 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed. 0 (B_0x0): The master operates in 7-bit addressing mode, 1 (B_0x1): The master operates in 10-bit addressing mode |
| HEAD10R | 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed. 0 (B_0x0): The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. 1 (B_0x1): The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. |
| START | Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing ‘1’ to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing ‘0’ to this bit has no effect. Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. Note: This bit has no effect when RELOAD is set. 0 (B_0x0): No Start generation. 1 (B_0x1): Restart/Start generation: |
| STOP | Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master mode: Note: Writing ‘0’ to this bit has no effect. 0 (B_0x0): No Stop generation. 1 (B_0x1): Stop generation after current byte transfer. |
| NACK | NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. Note: Writing ‘0’ to this bit has no effect. Note: This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. Note: When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value. 0 (B_0x0): an ACK is sent after current received byte. 1 (B_0x1): a NACK is sent after current received byte. |
| NBYTES | Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. |
| RELOAD | NBYTES reload mode This bit is set and cleared by software. 0 (B_0x0): The transfer is completed after the NBYTES data transfer (STOP or RESTART follows). 1 (B_0x1): The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low. |
| AUTOEND | Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set. 0 (B_0x0): software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. 1 (B_0x1): Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. |
| PECBYTE | Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. Note: Writing ‘0’ to this bit has no effect. Note: This bit has no effect when RELOAD is set. Note: This bit has no effect is slave mode when SBC=0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to Section 52.3: I2C implementation. 0 (B_0x0): No PEC transfer. 1 (B_0x1): PEC transmission/reception is requested |