Regviz

stm32 /stm32wb0 /STM32WB07 /LPUART /BRR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BRR

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https://regviz.com/r/stm32/stm32wb0/STM32WB05/LPUART/BRR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BRR

Description

BRR register

Fields

BRR

BRR[19:0]

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32