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stm32 /stm32wb0 /STM32WB07 /LPUART /ICR

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Interpret as ICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PECF)PECF 0 (FECF)FECF 0 (NECF)NECF 0 (ORECF)ORECF 0 (IDLECF)IDLECF 0 (TCCF)TCCF 0 (CTSCF)CTSCF 0 (CMCF)CMCF 0 (WUCF)WUCF

Description

ICR register

Fields

PECF

PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
FECF

FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register
NECF

NECF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register.
ORECF

ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
IDLECF

IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
TCCF

TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register
CTSCF

CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register
CMCF

CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register
WUCF

WUCF: Wakeup from Stop mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32