Regviz

stm32 /stm32wb0 /STM32WB07 /PWRC /CR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb0/STM32WB06/PWRC/CR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LPMS 0 (ENSDNBOR)ENSDNBOR 0 (B_0x0)APC

LPMS=B_0x0, APC=B_0x0

Description

CR1 register

Fields

LPMS

LPMS Low Power Mode Selection Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep.

0 (B_0x0): Deep Stop mode (default)

1 (B_0x1): Shutdown mode
ENSDNBOR

Enable BOR reset supervising during SHUTDOWN mode.
APC

APC Apply Pull-up and pull-down configuration from CPU

0 (B_0x0): the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os.

1 (B_0x1): the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32