RAMRET3=B_0x0, RAMRET1=B_0x0, PVDLS=B_0x0
CR2 register
| PVDE | PVDE Programmable Voltage Detector Enable When this bit is set the Power Voltage Detector is enabled |
| PVDLS | PVDLS[2:0] Programmable Voltage Detector Level selection then PVDO=1) 0 (B_0x0): 2.05 V - Lowest level 1 (B_0x1): 2.20 V 2 (B_0x2): 2.36 V 3 (B_0x3): 2.52 V 4 (B_0x4): 2.64 V 5 (B_0x5): 2.81 V 6 (B_0x6): 2.91 V - Highest level 7 (B_0x7): External input analog voltage (compare internally to VBGP; When external input <VBGP |
| RAMRET1 | RAMRET1: RAM1 retention during low power mode 0 (B_0x0): RAM1 bank is disabled during low power mode (by default) 1 (B_0x1): RAM1 bank is powered during low power mode |
| RAMRET2 | Enables the RAM2 bank retention in DEEPSTOP mode. |
| RAMRET3 | Enables the RAM3 bank retention in DEEPSTOP mode. 0 (B_0x0): Temperature sensor is disabled 1 (B_0x1): Temperature sensor is enabled |
| ENTS | Enable the temperature sensor. |
| LSILPMUFEN | LSI LPMU force enable. |