stm32 /stm32wb0 /STM32WB07 /PWRC /SR1

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Interpret as SR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)WUF0 0 (B_0x0)WUF1 0 (B_0x0)WUF2 0 (B_0x0)WUF3 0 (B_0x0)WUF4 0 (B_0x0)WUF5 0 (B_0x0)WUF6 0 (B_0x0)WUF7 0 (B_0x0)WUF8 0 (B_0x0)WUF9 0 (B_0x0)WUF10 0 (B_0x0)WUF11 0 (WBLEF)WBLEF 0 (WBLEHCPUF)WBLEHCPUF 0 (IWUF)IWUF

WUF0=B_0x0, WUF2=B_0x0, WUF5=B_0x0, WUF9=B_0x0, WUF3=B_0x0, WUF1=B_0x0, WUF8=B_0x0, WUF7=B_0x0, WUF11=B_0x0, WUF10=B_0x0, WUF6=B_0x0, WUF4=B_0x0

Description

SR1 register

Fields

WUF0

WUF0 WakeUp Flag 0 (PB0) This bit is set when a wakeup is detected on wakeup line 0. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF1

WUF1 WakeUp Flag 1 (PB1) This bit is set when a wakeup is detected on wakeup line 1. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF2

WUF2 WakeUp Flag 2 (PB2) This bit is set when a wakeup is detected on wakeup line 2. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF3

WUF3 WakeUp Flag 3 (PB3) This bit is set when a wakeup is detected on wakeup line 3. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF4

WUF4 WakeUp Flag 4 (PB4) This bit is set when a wakeup is detected on wakeup line 4. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF5

WUF5 WakeUp Flag 5 (PB5) This bit is set when a wakeup is detected on wakeup line 5. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF6

WUF6 WakeUp Flag 6 (PB6) This bit is set when a wakeup is detected on wakeup line 6. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF7

WUF7 WakeUp Flag 7 (PB7) This bit is set when a wakeup is detected on wakeup line 7. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF8

WUF8 WakeUp Flag 8 (PA8) This bit is set when a wakeup is detected on wakeup line 8. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF9

WUF9 WakeUp Flag 9 (PA9) This bit is set when a wakeup is detected on wakeup line 9. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF10

WUF10 WakeUp Flag 10 (PA10) This bit is set when a wakeup is detected on wakeup line 10. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WUF11

WUF11 WakeUp Flag 11 (PA11) This bit is set when a wakeup is detected on wakeup line 11. It is cleared by a reset pad or by writing 1 in this bit field. writting this bit, clears the interrupt:

0 (B_0x0): no effect

1 (B_0x1): clear the interrupt

WBLEF

WBLEF: BLE wakeup flag. 0: no wakeup from BLE occurred since last clear. 1: a wakeup from BLE occurred since last clear. Cleared by writing 1 in this bit.

WBLEHCPUF

WBLEHCPUF: BLE Host CPU wakeup flag. 0: no wakeup from BLE Host CPU occurred since last clear. 1: a wakeup from BLE Host CPU occurred since last clear. Cleared by writing 1 in this bit.

IWUF

IWUF: Internal wakeup flag (RTC). 0: no wakeup from RTC occurred since last clear. 1: a wakeup from RTC occurred since last clear. Note: The user must clear the RTC wakeup flag inside the RTC IP to clear this bit (mirror of the RTC wakeup line on the PWRC block).

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