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stm32 /stm32wb0 /STM32WB07 /RADIO /RXADC_ANA_USR

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Interpret as RXADC_ANA_USR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RFD_RXADC_DELAYTRIM_I 0RFD_RXADC_DELAYTRIM_Q 0 (RXADC_DELAYTRIM_I_TST_SEL)RXADC_DELAYTRIM_I_TST_SEL 0 (RXADC_DELAYTRIM_Q_TST_SEL)RXADC_DELAYTRIM_Q_TST_SEL

Description

RXADC_ANA_USR register

Fields

RFD_RXADC_DELAYTRIM_I

ADC loop delay control bits for I channel to apply when SW overload is enabled
RFD_RXADC_DELAYTRIM_Q

ADC loop delay control bits for Q channel to apply when SW overload is enabled
RXADC_DELAYTRIM_I_TST_SEL

Enable the SW overload on RXADX delay trimming
RXADC_DELAYTRIM_Q_TST_SEL

Enable the SW overload on RXADX delay trimming

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32