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stm32 /stm32wb0 /STM32WB07 /RCC /APB0ENR

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Interpret as APB0ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM1EN 0 (B_0x0)SYSCFGEN 0 (B_0x0)RTCEN 0 (B_0x0)WDGEN

RTCEN=B_0x0, WDGEN=B_0x0, SYSCFGEN=B_0x0, TIM1EN=B_0x0

Description

APB0ENR register

Fields

TIM1EN

TIM1 enable

0 (B_0x0): does not enable

1 (B_0x1): enable
SYSCFGEN

SYSTEM CONFIG enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
RTCEN

RTC clock enable Set and enable by software. Reset source only for this field: PORESETn

0 (B_0x0): does not enable

1 (B_0x1): enable
WDGEN

Watchdog clock enable. Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32