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stm32 /stm32wb0 /STM32WB07 /RCC /APB1RSTR

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Interpret as APB1RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI1RST)SPI1RST 0 (ADCRST)ADCRST 0 (B_0x0)LPUARTRST 0 (B_0x0)USARTRST 0 (SPI2RST)SPI2RST 0 (B_0x0)SPI3RST 0 (B_0x0)I2C1RST 0 (I2C2RST)I2C2RST

USARTRST=B_0x0, I2C1RST=B_0x0, LPUARTRST=B_0x0, SPI3RST=B_0x0

Description

APB1RSTR register

Fields

SPI1RST

SPI1 reset
ADCRST

ADC reset.
LPUARTRST

LPUART reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
USARTRST

USART reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
SPI2RST

SPI2 reset.
SPI3RST

SPI3 reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
I2C1RST

I2C1 reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
I2C2RST

2C2 reset.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32