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stm32 /stm32wb0 /STM32WB07 /RCC /APB2ENR

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Interpret as APB2ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MRBLEEN 0 (B_0x0)CLKBLEDIV

CLKBLEDIV=B_0x0, MRBLEEN=B_0x0

Description

APB2ENR register

Fields

MRBLEEN

MR_BLE enable

0 (B_0x0): MR_BLE IP is clock gated

1 (B_0x1): MR_BLE IP is clocked
CLKBLEDIV

MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1

0 (B_0x0): 32MHz

1 (B_0x1): 16MHz

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32