RMVF=B_0x0, WDGRSTF=B_0x0, LOCKUPRSTF=B_0x0, SFTRSTF=B_0x0, PORRSTF=B_0x0, PADRSTF=B_0x0
CSR register
| RMVF | Remove reset flag Set by software to clear the value of the reset flags. It auto clears by HW after clearing reason flags 0 (B_0x0): Nothing done 1 (B_0x1): Reset the value of the reset flags |
| PADRSTF | SYSTEM reset flag Reset by software by writing the RMVF bit. Set by hardware when a reset from pad occurs. 0 (B_0x0): No reset from pad occurred 1 (B_0x1): Reset from pad occurred |
| PORRSTF | POWER reset flag Reset by software by writing the RMVF bit. Set by hardware when a power reset occurs from LPMURESET block. 0 (B_0x0): No POWER reset occurred 1 (B_0x1): POWER reset occurred |
| SFTRSTF | Software reset flag Reset by software by writing the RMVF bit. Set by hardware when a software reset occurs. 0 (B_0x0): No software reset occurred 1 (B_0x1): Software reset occurred |
| WDGRSTF | Watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a watchdog reset from V33 domain occurs. 0 (B_0x0): No watchdog reset occurred 1 (B_0x1): Watchdog reset occurred |
| LOCKUPRSTF | LOCK UP reset flag from CM0 Reset by software by writing the RMVF bit. Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. 0 (B_0x0): No lockup reset occurred 1 (B_0x1): lockup reset occurred |