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stm32 /stm32wb0 /STM32WB09 /RCC /APB1ENR

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Interpret as APB1ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ADCDIGEN 0 (B_0x0)ADCANAEN 0 (B_0x0)LPUARTEN 0 (B_0x0)USART1EN 0 (B_0x0)SPI3EN 0 (B_0x0)I2C1EN

SPI3EN=B_0x0, ADCANAEN=B_0x0, USART1EN=B_0x0, LPUARTEN=B_0x0, ADCDIGEN=B_0x0, I2C1EN=B_0x0

Description

APB1ENR register

Fields

ADCDIGEN

AUXADC clock enable for Aux-ADC digital clock Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
ADCANAEN

ADC clock enable for Aux-ADC analog clock Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
LPUARTEN

LPUART clock enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
USART1EN

USART clock enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
SPI3EN

SPI3 clock enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable
I2C1EN

I2C1 clock enable Set and enable by software.

0 (B_0x0): does not enable

1 (B_0x1): enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32