CLKSLOWSEL=B_0x0, STOPHSI=B_0x0, LCOSEL=B_0x0, IOBOOSTCLKEXTEN=B_0x0, CCOPRE=B_0x0, SMPSINV=B_0x0, SMPSDIV=B_0x0, IOBOOSTEN=B_0x0, HSESEL=B_0x0, SPI3I2SCLKSEL=B_0x0, MCOSEL=B_0x0, HSESEL_STATUS=B_0x0, LPUCLKSEL=B_0x0
CFGR register
| SMPSINV | bit to control inversion of the SMPS clock 0 (B_0x0): SMPS clock not inverted (default value) 1 (B_0x1): SMPS clock inverted (for debug) |
| HSESEL | Clock source selection request: 0 (B_0x0): HSI clock source is requested (default) 1 (B_0x1): HSE clock source is requested |
| STOPHSI | Stop HSI clock source request 0 (B_0x0): HSI is enabled (default) 1 (B_0x1): disable HSI is requested |
| HSESEL_STATUS | Clock source selection Status 0 (B_0x0): HSI clock source is requested (default) 1 (B_0x1): HSE clock source is requested |
| CLKSYSDIV | CLKSYSDIV: system clock divided factor from HSI_64M. 000: system clock frequency is 64 MHz (not available when HSESEL=1) 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz * 100: system clock frequency is 4 MHz * 101: system clock frequency is 2 MHz * 110: system clock frequency is 1 MHz * 111: not used. *: If RCC_APB2ENR.MRBLEEN bit is set, writing in CLKSYSDIV one of those values is replaced by a 010b = 16 MHz writing at hardware level. Warning: if the software programs the 64 MHz frequency target while the RCC_CFGR.HSESEL=1, the hardware will switch the system clock tree on HSI64MPLL again (and restart HSIPLL64M analog block if RCC_CFGR.STOPHSI=1) To switch the system frequency between 64 / 32 / 16 MHz without risk when the MR_BLE is used, prefer the RCC_CSCMDR register to change the system frequency. the MR_BLE frequency must always be equal or less than the CPU/system clock to have functional radio. |
| CLKSYSDIV_STATUS | CLKSYSDIV_STATUS: system clock frequency status Set and cleared by hardware to indicate the actual system clock frequency. This register must be read to be sure that the new frequency, selected by CLKSYSDIV, has been applied. 000: system clock frequency is 64 MHz 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz 100: system clock frequency is 4 MHz 101: system clock frequency is 2 MHz 110: system clock frequency is 1 MHz 111: not used. The actual clock frequency switching can be delayed of up to 128 system clock cycles, depending on the RCC internal counter status at the moment the new CLKSYSDIV is applied |
| SMPSDIV | SMPS clock prescaling factor to generate 4MHz or 8MHz 0 (B_0x0): div 2 when ANADIV=2 or 4 (default ) 1 (B_0x1): div 4 when ANADIV=1 or 2 |
| LPUCLKSEL | Selection of LPUART clock: 0 (B_0x0): 16MHz peripheral clock (default) 1 (B_0x1): LSE clock |
| CLKSLOWSEL | slow clock source selection Set by software to select the clock source. This is no glitch free mechanism Reset source only for this field: PORESETn 0 (B_0x0): LSILMPU oscillator clock (default) 1 (B_0x1): LSE oscillator clock used as slow clock 2 (B_0x2): LSI oscillator clock used as slow clock 3 (B_0x3): HSI_64M divided by 2048 used as slow clock |
| IOBOOSTEN | IO BOOSTER enable Set and reset by software. 0 (B_0x0): does not enable IO BOOSTER 1 (B_0x1): enable IO BOOSTER |
| IOBOOSTCLKEXTEN | IO BOOSTER clock enable as external clock Set and reset by software. 0 (B_0x0): does not use rcc clock (default) 1 (B_0x1): uses rcc clock |
| LCOEN | LCO output enable |
| SPI3I2SCLKSEL | Selection of I2S1 clock: 1x:64MHz peripheral clock 0 (B_0x0): 16MHz peripheral clock (default) 1 (B_0x1): 32MHz peripheral clock |
| LCOSEL | Low speed Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. Reset source only for this field: PORESETn 0 (B_0x0): LCO output disabled, no clock on LCO 1 (B_0x1): internal 32 KHz (LSI_LPMU) oscillator clock selected 2 (B_0x2): internal 32 KHz (LSI) oscillator clock selected 3 (B_0x3): external 32 KHz (LSE) oscillator clock selected |
| MCOSEL | Main Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. 0 (B_0x0): MCO output disabled, no clock on MCO 1 (B_0x1): system clock selected 2 (B_0x2): na 3 (B_0x3): internal RC 64 MHz (HSI) oscillator clock selected 4 (B_0x4): external oscillator (HSE) clock selected 5 (B_0x5): internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected 6 (B_0x6): SMPS clock selected 7 (B_0x7): AUX ADC ANA clock selected |
| CCOPRE | Configurable Clock Output Prescaler. Set and reset by software. Glitches propagation if CCOPRE is modified after CCO output is enabled. Others: not used 0 (B_0x0): CCO clock is divided by 1 1 (B_0x1): CCO clock is divided by 2 2 (B_0x2): CCO clock is divided by 4 3 (B_0x3): CCO clock is divided by 8 4 (B_0x4): CCO clock is divided by 16 |