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stm32 /stm32wb0 /STM32WB09 /RCC /CIER

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Interpret as CIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LSIRDYIE 0 (B_0x0)LSERDYIE 0 (B_0x0)HSIRDYIE 0 (B_0x0)HSERDYIE 0 (B_0x0)HSIPLLRDYIE 0 (B_0x0)HSIPLLUNLOCKDETIE 0 (B_0x0)RTCRSTIE 0 (B_0x0)WDGRSTIE 0 (B_0x0)LPURSTIE

LPURSTIE=B_0x0, HSIPLLRDYIE=B_0x0, LSERDYIE=B_0x0, LSIRDYIE=B_0x0, HSIRDYIE=B_0x0, WDGRSTIE=B_0x0, HSIPLLUNLOCKDETIE=B_0x0, RTCRSTIE=B_0x0, HSERDYIE=B_0x0

Description

CIER register

Fields

LSIRDYIE

LSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization.

0 (B_0x0): LSI ready interrupt disabled

1 (B_0x1): LSI ready interrupt enabled
LSERDYIE

LSE Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization.

0 (B_0x0): LSE ready interrupt disabled

1 (B_0x1): LSE ready interrupt enabled
HSIRDYIE

HSI Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization.

0 (B_0x0): HSI ready interrupt disabled

1 (B_0x1): HSI ready interrupt enabled
HSERDYIE

HSE Ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization.

0 (B_0x0): HSE ready interrupt disabled

1 (B_0x1): HSE ready interrupt enabled
HSIPLLRDYIE

HSI PLL Ready Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE.

0 (B_0x0): HSI PLL ready interrupt disabled

1 (B_0x1): HSI PLL ready interrupt enabled
HSIPLLUNLOCKDETIE

HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock.

0 (B_0x0): HSI PLL unlock detection interrupt disabled

1 (B_0x1): HSI PLL unlock detection interrupt enabled
RTCRSTIE

RTCRSTIE: RTC reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the RTC reset end.

0 (B_0x0): HSI PLL unlock detection interrupt disabled

1 (B_0x1): HSI PLL unlock detection interrupt enabled
WDGRSTIE

WDGRSTIE: Watchdog reset end Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the watchdog reset end.

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled
LPURSTIE

LPURSTIE: LPUART reset release interrupt enable.

0 (B_0x0): LPUART reset release interrupt is disabled

1 (B_0x1): LPUART reset release interrupt is enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32