Regviz

stm32 /stm32wb0 /STM32WB09 /RCC /CSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb0/STM32WB05/RCC/CSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RMVF 0 (B_0x0)PADRSTF 0 (B_0x0)PORRSTF 0 (B_0x0)SFTRSTF 0 (B_0x0)WDGRSTF 0 (B_0x0)LOCKUPRSTF

WDGRSTF=B_0x0, RMVF=B_0x0, LOCKUPRSTF=B_0x0, SFTRSTF=B_0x0, PORRSTF=B_0x0, PADRSTF=B_0x0

Description

CSR register

Fields

RMVF

Remove reset flag Set by software to clear the value of the reset flags. It auto clears by HW after clearing reason flags

0 (B_0x0): Nothing done

1 (B_0x1): Reset the value of the reset flags
PADRSTF

SYSTEM reset flag Reset by software by writing the RMVF bit. Set by hardware when a reset from pad occurs.

0 (B_0x0): No reset from pad occurred

1 (B_0x1): Reset from pad occurred
PORRSTF

POWER reset flag Reset by software by writing the RMVF bit. Set by hardware when a power reset occurs from LPMURESET block.

0 (B_0x0): No POWER reset occurred

1 (B_0x1): POWER reset occurred
SFTRSTF

Software reset flag Reset by software by writing the RMVF bit. Set by hardware when a software reset occurs.

0 (B_0x0): No software reset occurred

1 (B_0x1): Software reset occurred
WDGRSTF

Watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a watchdog reset from V33 domain occurs.

0 (B_0x0): No watchdog reset occurred

1 (B_0x1): Watchdog reset occurred
LOCKUPRSTF

LOCK UP reset flag from CM0 Reset by software by writing the RMVF bit. Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals.

0 (B_0x0): No lockup reset occurred

1 (B_0x1): lockup reset occurred

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32