CHSIDE=B_0x0, OVR=B_0x0, RXNE=B_0x0, TXE=B_0x0, MODF=B_0x0, FRLVL=B_0x0, FRE=B_0x0, FTLVL=B_0x0, BSY=B_0x0, CRCERR=B_0x0, UDR=B_0x0
SPI status register
| RXNE | Receive buffer not empty 0 (B_0x0): Rx buffer empty 1 (B_0x1): Rx buffer not empty |
| TXE | Transmit buffer empty 0 (B_0x0): Tx buffer not empty 1 (B_0x1): Tx buffer empty |
| CHSIDE | Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode. 0 (B_0x0): Channel Left has to be transmitted or has been received 1 (B_0x1): Channel Right has to be transmitted or has been received |
| UDR | Underrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. Note: This bit is not used in SPI mode. 0 (B_0x0): No underrun occurred 1 (B_0x1): Underrun occurred |
| CRCERR | CRC error flag Note: This flag is set by hardware and cleared by software writing 0. Note: This bit is not used in I2S mode. 0 (B_0x0): CRC value received matches the SPIx_RXCRCR value 1 (B_0x1): CRC value received does not match the SPIx_RXCRCR value |
| MODF | Mode fault This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. Note: This bit is not used in I2S mode. 0 (B_0x0): No mode fault occurred 1 (B_0x1): Mode fault occurred |
| OVR | Overrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. 0 (B_0x0): No overrun occurred 1 (B_0x1): Overrun occurred |
| BSY | Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789. 0 (B_0x0): SPI (or I2S) not busy 1 (B_0x1): SPI (or I2S) is busy in communication or Tx buffer is not empty |
| FRE | Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. This flag is set by hardware and reset when SPIx_SR is read by software. 0 (B_0x0): No frame format error 1 (B_0x1): A frame format error occurred |
| FRLVL | FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled. 0 (B_0x0): FIFO empty 1 (B_0x1): 1/4 FIFO 2 (B_0x2): 1/2 FIFO 3 (B_0x3): FIFO full |
| FTLVL | FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode. 0 (B_0x0): FIFO empty 1 (B_0x1): 1/4 FIFO 2 (B_0x2): 1/2 FIFO 3 (B_0x3): FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) |