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stm32 /stm32wb0 /STM32WB09 /USART /BRR

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Interpret as BRR

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https://regviz.com/r/stm32/stm32wb0/STM32WB05/USART/BRR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BRR

Description

BRR register

Fields

BRR

BRR[15:4] BRR[15:4] = USARTDIV[15:4]BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32