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stm32 /stm32wba5 /STM32WBA50 /FLASH /FLASH_OPSR

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Interpret as FLASH_OPSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDR_OP0 (SYSF_OP)SYSF_OP 0 (B_0x0)CODE_OP

CODE_OP=B_0x0

Description

FLASH operation status register

Fields

ADDR_OP

Interrupted operation address This field indicates which address in the Flash memory was accessed when reset occurred. The address is given relative to the Flash base address, from offset 0x00000 to 0xFFFF0. Note that bit 19 is reserved on STM32WBAxEx devices.
SYSF_OP

Operation in system Flash memory interrupted This bit indicates that the reset occurred during an operation in the system Flash memory.
CODE_OP

Flash memory operation code This field indicates which Flash memory operation has been interrupted by a system reset:

0 (B_0x0): No Flash operation interrupted by previous reset

1 (B_0x1): Single write operation interrupted

2 (B_0x2): Burst write operation interrupted

3 (B_0x3): Page erase operation interrupted

5 (B_0x5): Mass erase operation interrupted

6 (B_0x6): Option change operation interrupted

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32