RegViz: Visualize PWR_IORETENRB Bitfield

stm32 /stm32wba5 /STM32WBA50 /PWR /PWR_IORETENRB

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Interpret as PWR_IORETENRB

EN4=B_0x0, EN2=B_0x0, EN1=B_0x0, EN14=B_0x0, EN3=B_0x0, EN11=B_0x0, EN6=B_0x0, EN8=B_0x0, EN9=B_0x0, EN7=B_0x0, EN15=B_0x0, EN10=B_0x0, EN12=B_0x0, EN5=B_0x0, EN13=B_0x0, EN0=B_0x0

Description

PWR port B Standby IO retention enable register

Fields

EN0	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN1	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN2	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN3	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN4	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN5	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN6	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN7	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN8	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN9	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN10	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN11	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN12	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN13	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN14	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.
EN15	Port B Standby GPIO retention enable Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PBy Standby GPIO retention feature disabled. 1 (B_0x1): PBy Standby GPIO retention feature enabled.

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