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stm32 /stm32wba5 /STM32WBA50 /RAMCFG /RAMCFG_M2IER

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Interpret as RAMCFG_M2IER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PEIE 0 (B_0x0)PENMI

PEIE=B_0x0, PENMI=B_0x0

Description

RAMCFG SRAM2 interrupt enable register

Fields

PEIE

Parity error interrupt enable

0 (B_0x0): Parity error interrupt disabled

1 (B_0x1): Parity error interrupt enabled
PENMI

Parity error NMI. This bit is set by software and cleared only by a global RAMCFG reset Note: When PENMI bit is set, the RAMCFG maskable interrupt is not generated for a parity error whatever PEIE bit value.

0 (B_0x0): NMI not generated in case of parity error

1 (B_0x1): NMI generated in case of parity error

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32