USART1SEL=B_0x0, TIMICSEL=B_0x0, I2C1SEL=B_0x0, USART2SEL=B_0x0, SPI1SEL=B_0x0, LPTIM2SEL=B_0x0, SYSTICKSEL=B_0x0
RCC peripherals independent clock configuration register 1
| USART1SEL | USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE. 0 (B_0x0): pclk2 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| USART2SEL | USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE. 0 (B_0x0): pclk1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| I2C1SEL | I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16. 0 (B_0x0): pclk1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected |
| LPTIM2SEL | Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1. 0 (B_0x0): pclk1 selected 1 (B_0x1): LSI selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| SPI1SEL | SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16. 0 (B_0x0): pclk2 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected |
| SYSTICKSEL | SysTick clock source selection These bits are used to select the SysTick clock source. Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry. 0 (B_0x0): hclk1 divided by 8 selected 1 (B_0x1): LSI selected 2 (B_0x2): LSE selected |
| TIMICSEL | Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI16/256. When TIMICSEL is cleared, the HSI16, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division. 0 (B_0x0): HSI16 divider disabled 1 (B_0x1): HSI16/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture |