DMAINEN=B_0x0, DMAOUTEN=B_0x0, GCMPH=B_0x0, MODE=B_0x0, KMOD=B_0x0, NPBLB=B_0x0, KEYSIZE=B_0x0, CHMOD=B_0x0, EN=B_0x0, DATATYPE=B_0x0
AES control register
| EN | Enable This bit enables/disables the AES peripheral. At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (MODE[1:0] at 01) and upon the completion of GCM/GMAC/CCM initialization phase. The bit cannot be set as long as KEYVALID=0. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DATATYPE | Data type This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping. This swapping is defined in Section23.4.17: AES data registers and data swapping. Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 0 (B_0x0): No swapping (32-bit data). 1 (B_0x1): Half-word swapping (16-bit data) 2 (B_0x2): Byte swapping (8-bit data) 3 (B_0x3): Bit-level swapping |
| MODE | Operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 0 (B_0x0): Encryption 1 (B_0x1): Key derivation (or key preparation), for ECB/CBC decryption only 2 (B_0x2): Decryption |
| CHMOD | CHMOD[1:0]: Chaining mode This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 0 (B_0x0): Electronic codebook (ECB) 1 (B_0x1): Cipher-block chaining (CBC) 2 (B_0x2): Counter mode (CTR) 3 (B_0x3): Galois counter mode (GCM) and Galois message authentication code (GMAC) |
| DMAINEN | DMA input enable When this bit is set, DMA requests are automatically generated by the peripheral during the input data phase. Setting this bit is ignored when MODE[1:0] is at 01 (key derivation). 0 (B_0x0): DMA for incoming data transfer is disabled 1 (B_0x1): DMA for incoming data transfer is enabled |
| DMAOUTEN | DMA output enable When this bit is set, DMA requests are automatically generated by the peripheral during the output data phase. Setting this bit is ignored when MODE[1:0] is at 01 (key derivation). 0 (B_0x0): DMA for outgoing data transfer is disabled 1 (B_0x1): DMA for outgoing data transfer is enabled |
| GCMPH | GCM or CCM phase selection This bitfield selects the phase, applicable only with GCM, GMAC or CCM chaining modes. This bitfield has no effect if GCM, GMAC or CCM algorithm is not selected with CHMOD[2:0]. 0 (B_0x0): Initialization phase 1 (B_0x1): Header phase 2 (B_0x2): Payload phase 3 (B_0x3): Final phase |
| CHMOD_1 | CHMOD[2] |
| KEYSIZE | Key size selection This bitfield defines the key length in bits of the key used by AES. Attempts to write the bit are ignored when BUSY is set, as well as when the EN is set before the write access and it is not cleared by that write access. 0 (B_0x0): 128-bit 1 (B_0x1): 256-bit |
| NPBLB | Number of padding bytes in last block This padding information must be filled by software before processing the last block of GCM payload encryption or CCM payload decryption, otherwise authentication tag computation is incorrect. … 0 (B_0x0): All bytes are valid (no padding) 1 (B_0x1): Padding for the last LSB byte 15 (B_0xF): Padding for the 15 LSB bytes of last block. |
| KMOD | Key mode selection The bitfield defines how the AES key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set, as well as when EN is set before the write access and it is not cleared by that write access. 0 (B_0x0): Normal key mode. Key registers are freely usable. 2 (B_0x2): Shared key mode. If shared key mode is properly initialized in SAES peripheral, the AES peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in AES key registers when BUSY bit is cleared and KEYVALID is set in the AES_SR register. Key error flag KEIF is set otherwise in the AES_ISR register. |
| IPRST | AES peripheral software reset Setting the bit resets the AES peripheral, putting all registers to their default values, except the IPRST bit itself. Hence, any key-relative data are lost. For this reason, it is recommended to set the bit before handing over the AES to a less secure application. The bit must be low while writing any configuration registers. |