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stm32 /stm32wba5 /STM32WBA52 /DBGMCU /DBGMCU_AHB1FZR

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Interpret as DBGMCU_AHB1FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBG_GPDMA1_CH0_STOP 0 (B_0x0)DBG_GPDMA1_CH1_STOP 0 (B_0x0)DBG_GPDMA1_CH2_STOP 0 (B_0x0)DBG_GPDMA1_CH3_STOP 0 (B_0x0)DBG_GPDMA1_CH4_STOP 0 (B_0x0)DBG_GPDMA1_CH5_STOP 0 (B_0x0)DBG_GPDMA1_CH6_STOP 0 (B_0x0)DBG_GPDMA1_CH7_STOP

DBG_GPDMA1_CH7_STOP=B_0x0, DBG_GPDMA1_CH2_STOP=B_0x0, DBG_GPDMA1_CH4_STOP=B_0x0, DBG_GPDMA1_CH6_STOP=B_0x0, DBG_GPDMA1_CH0_STOP=B_0x0, DBG_GPDMA1_CH5_STOP=B_0x0, DBG_GPDMA1_CH1_STOP=B_0x0, DBG_GPDMA1_CH3_STOP=B_0x0

Description

DBGMCU AHB1 peripheral freeze register

Fields

DBG_GPDMA1_CH0_STOP

GPDMA 1 channel 0 stop in CPU debug

Write access can be protected by GPDMA_SECCFGR.SEC0.

0 (B_0x0): Normal operation. GPDMA 1 channel 0 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. GPDMA 1 channel 0 is frozen while CPU is in debug mode.
DBG_GPDMA1_CH1_STOP

GPDMA 1 channel 1 stop in CPU debug

Write access can be protected by GPDMA_SECCFGR.SEC1.

0 (B_0x0): Normal operation. GPDMA 1 channel 1 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. GPDMA 1 channel 1 is frozen while CPU is in debug mode.
DBG_GPDMA1_CH2_STOP

GPDMA 1 channel 2 stop in CPU debug

Write access can be protected by GPDMA_SECCFGR.SEC2.

0 (B_0x0): Normal operation. GPDMA 1 channel 2 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. GPDMA 1 channel 2 is frozen while CPU is in debug mode.
DBG_GPDMA1_CH3_STOP

GPDMA 1 channel 3 stop in CPU debug

Write access can be protected by GPDMA_SECCFGR.SEC3.

0 (B_0x0): Normal operation. GPDMA 1 channel 3 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. GPDMA 1 channel 3 is frozen while CPU is in debug mode.
DBG_GPDMA1_CH4_STOP

GPDMA 1 channel 4 stop in CPU debug

Write access can be protected by GPDMA_SECCFGR.SEC4.

0 (B_0x0): Normal operation. GPDMA 1 channel 4 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. GPDMA 1 channel 4 is frozen while CPU is in debug mode.
DBG_GPDMA1_CH5_STOP

GPDMA 1 channel 5 stop in CPU debug

Write access can be protected by GPDMA_SECCFGR.SEC5.

0 (B_0x0): Normal operation. GPDMA 1 channel 5 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. GPDMA 1 channel 5 is frozen while CPU is in debug mode.
DBG_GPDMA1_CH6_STOP

GPDMA 1 channel 6 stop in CPU debug

Write access can be protected by GPDMA_SECCFGR.SEC6.

0 (B_0x0): Normal operation. GPDMA 1 channel 6 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. GPDMA 1 channel 6 is frozen while CPU is in debug mode.
DBG_GPDMA1_CH7_STOP

GPDMA 1 channel 7 stop in CPU debug

Write access can be protected by GPDMA_SECCFGR.SEC7.

0 (B_0x0): Normal operation. GPDMA 1 channel 7 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. GPDMA 1 channel 7 is frozen while CPU is in debug mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32