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stm32 /stm32wba5 /STM32WBA52 /DBGMCU /DBGMCU_APB2FZR

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Interpret as DBGMCU_APB2FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBG_TIM1_STOP 0 (B_0x0)DBG_TIM16_STOP 0 (B_0x0)DBG_TIM17_STOP

DBG_TIM16_STOP=B_0x0, DBG_TIM17_STOP=B_0x0, DBG_TIM1_STOP=B_0x0

Description

DBGMCU APB2 peripheral freeze register

Fields

DBG_TIM1_STOP

TIM1 stop in CPU debug

Write access can be protected by GTZC_TZSC.TIM1SEC.

0 (B_0x0): Normal operation. TIM1 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. TIM1 is frozen while CPU is in debug mode.
DBG_TIM16_STOP

TIM16 stop in CPU debug

Write access can be protected by GTZC_TZSC.TIM16SEC.

0 (B_0x0): Normal operation. TIM16 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. TIM16 is frozen while CPU is in debug mode.
DBG_TIM17_STOP

TIM17 stop in CPU debug

Write access can be protected by GTZC_TZSC.TIM17SEC.

0 (B_0x0): Normal operation. TIM17 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. TIM17 is frozen while CPU is in debug mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32