ERRIE=B_0x0, PNB=B_0x0, OBL_LAUNCH=B_0x0, PER=B_0x0, PG=B_0x0, EOPIE=B_0x0
FLASH control register
| PG | Non-secure programming 0 (B_0x0): Non-secure Flash programming disabled 1 (B_0x1): Non-secure Flash programming enabled |
| PER | Non-secure page erase 0 (B_0x0): Non-secure page erase disabled 1 (B_0x1): Non-secure page erase enabled |
| MER | Non-secure Flash mass erase This bit triggers the Flash non-secure mass erase (all Flash user pages) when set. |
| PNB | Non-secure page number selection These bits select the page to erase. … Note that bit 9 is reserved on STM32WBA5xEx devices. 0 (B_0x0): page 0 1 (B_0x1): page 1 127 (B_0x7F): page 127 |
| BWR | Non-secure burst write programming mode When set, this bit selects the burst write programming mode. |
| STRT | Non-secure operation start This bit triggers a non-secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR. |
| OPTSTRT | Options modification start This bit triggers an option bytes erase and program operation when set. This bit is write-protected with OPTLOCK… This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR. |
| EOPIE | Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1. 0 (B_0x0): Non-secure EOP Interrupt disabled 1 (B_0x1): Non-secure EOP Interrupt enabled |
| ERRIE | Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1. 0 (B_0x0): Non-secure OPERR error interrupt disabled 1 (B_0x1): Non-secure OPERR error interrupt enabled |
| OBL_LAUNCH | Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. This bit is write-protected with OPTLOCK. Note: The LSE oscillator must be disabled, LSEON = 0 and LSERDY = 0, before starting OBL_LAUNCH. 0 (B_0x0): Option byte loading complete 1 (B_0x1): Option byte loading requested |
| OPTLOCK | Option lock This bit is set only. When set, the FLASH_NSCR1.OPTSRT and OBL_LAUNCH bits concerning user options write access is locked. This bit is cleared by hardware after detecting the unlock sequence in FLASH_OPTKEYR. The FLASH_NSCR1.LOCK bit must be cleared before doing the FLASH_OPTKEYR unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next reset. |
| LOCK | Non-secure lock This bit is set only. When set, the FLASH_NSCR1 register write access is locked. This bit is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. |