stm32 /stm32wba5 /STM32WBA52 /GTZC1_TZIC /GTZC1_TZIC_IER1

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Interpret as GTZC1_TZIC_IER1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM2IE 0 (B_0x0)TIM3IE 0 (B_0x0)WWDGIE 0 (B_0x0)IWDGIE 0 (B_0x0)USART2IE 0 (B_0x0)I2C1IE 0 (B_0x0)LPTIM2IE

USART2IE=B_0x0, WWDGIE=B_0x0, IWDGIE=B_0x0, TIM2IE=B_0x0, I2C1IE=B_0x0, TIM3IE=B_0x0, LPTIM2IE=B_0x0

Description

TZIC interrupt enable register 1

Fields

TIM2IE

illegal access interrupt enable for TIM2

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled

TIM3IE

illegal access interrupt enable for TIM3

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled

WWDGIE

illegal access interrupt enable for WWDG

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled

IWDGIE

illegal access interrupt enable for IWDG

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled

USART2IE

illegal access interrupt enable for USART2

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled

I2C1IE

illegal access interrupt enable for I2C1

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled

LPTIM2IE

illegal access interrupt enable for LPTIM2

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled

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