stm32 /stm32wba5 /STM32WBA52 /HSEM /HSEM_ICR

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Interpret as HSEM_ICR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ISC

ISC=B_0x0

Description

HSEM non-secure interrupt clear register

Fields

ISC

Non-secure Interrupt semaphore x clear bit This bit is written by software, and is always read 0. When semaphore x SECx is disabled, bit x can be accessed with secure and non-secure access. When semaphore x SECx is enabled, bit x cannot be accessed, write to this bit is discarded. When semaphore x PRIVx is disabled, bit x can be accessed with privileged and unprivileged access. When semaphore x PRIVx is enabled, bit x can only be accessed with privileged access. Unprivileged write to this bit is discarded.

0 (B_0x0): non-secure Interrupt semaphore x status ISFx and masked status MISFx not affected.

1 (B_0x1): non-secure Interrupt semaphore x status ISFx and masked status MISFx cleared.

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