HSEM_SISR

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Interpret as HSEM_SISR

SISF=B_0x0

Description

HSEM secure interrupt status register

Fields

SISF

Secure interrupt semaphore x status bit before enable (mask) This bit is set by hardware and read only by software. Bit is cleared by software writing the corresponding HSEM_SCnICR bit x. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. Secure unprivileged read return 0 value.

0 (B_0x0): Secure interrupt semaphore x status, no interrupt pending.

1 (B_0x1): Secure interrupt semaphore x status, interrupt pending.

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