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stm32 /stm32wba5 /STM32WBA52 /PWR /PWR_CR3

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Interpret as PWR_CR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (REGSEL)REGSEL 0 (B_0x0)FSTEN

FSTEN=B_0x0

Description

PWR control register 3

Fields

REGSEL

Regulator selection
FSTEN

Fast soft start

0 (B_0x0): LDO fast startup disabled (limited inrush current)

1 (B_0x1): LDO fast startup enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32