PWR_IORETENRH

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Interpret as PWR_IORETENRH

EN3=B_0x0

Description

PWR port H Standby IO retention enable register

Fields

EN3

Port H Standby GPIO retention enable Access can be secured by GPIOH SEC3. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): PHy Standby GPIO retention feature disabled.

1 (B_0x1): PHy Standby GPIO retention feature enabled.

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