RegViz: Visualize PWR_IORETRA Bitfield

stm32 /stm32wba5 /STM32WBA52 /PWR /PWR_IORETRA

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Interpret as PWR_IORETRA

RET14=B_0x0, RET12=B_0x0, RET9=B_0x0, RET3=B_0x0, RET1=B_0x0, RET11=B_0x0, RET7=B_0x0, RET8=B_0x0, RET15=B_0x0, RET0=B_0x0, RET6=B_0x0, RET5=B_0x0, RET13=B_0x0, RET10=B_0x0, RET2=B_0x0

Description

PWR port A Standby IO retention status register

Fields

RET0	Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET1	Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET2	Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET3	Port A Standby GPIO retention active Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET5	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET6	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET7	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET8	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET9	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET10	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET11	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET12	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET13	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET14	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
RET15	Port A Standby GPIO retention active Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PAy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.

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