RET15=B_0x0, RET13=B_0x0, RET14=B_0x0
PWR port C Standby IO retention status register
| RET13 | Port C Standby GPIO retention active Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PCy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PCy is enabled in PWR_IORETENRC and Standby mode is entered. Standby GPIO retention PCy active. |
| RET14 | Port C Standby GPIO retention active Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PCy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PCy is enabled in PWR_IORETENRC and Standby mode is entered. Standby GPIO retention PCy active. |
| RET15 | Port C Standby GPIO retention active Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PCy disabled. 1 (B_0x1): Set by hardware when Standby GPIO PCy is enabled in PWR_IORETENRC and Standby mode is entered. Standby GPIO retention PCy active. |